The trend in semiconductor device fabrication towards increasing density of circuit components requires that smaller areas of the circuit be devoted to isolation of the circuit components and capacitive storage devices. The need to reduce the surface area used for circuit components such as isolation structures and large area capacitor devices has resulted in the development of structures vertically oriented with respect to the plane of the substrate surface. These vertical structures typically consist of some type of trench structure in the semiconductor substrate and positioned between charge carrying components of adjacent transistors. The utilization of a trench structure enables the formation of a structure having large volume while minimizing the amount of surface area consumed.
The formation of vertically oriented isolation structures does not eliminate the possibility of current leakage paths. Accordingly, various isolation techniques have been developed and are used in advanced integrated circuitry to electrically isolate the various devices in the semiconductor substrate. One example of such an isolation technique is shallow trench isolation (STI), which is used in IC chips to provide higher device densities and better planarity than other isolation methods. In this technique, a STI area is defined to form isolation trenches surrounded by areas of wafer having a pad oxide layer and a polish-stop nitride layer on the surface. The isolation trench is then thermally oxidized to form a thin oxide layer on the isolation trench surfaces. A thin nitride layer is often deposited inside the isolation trench surfaces to prevent stress during the subsequent oxidation steps because the stress causes dislocations in the silicon wafer. Then, the isolation trench is filled with a chemical vapor deposited (CVD) oxide and chemically mechanically polished (CMP) back to the polish-stop nitride layer to form a planar surface. The polish-stop nitride layer is then removed. At this time, if there is a nitride liner, exposed areas of the nitride liner are etched back as well, which creates a divot. Even without a nitride liner, a divot can still form in the gate surface adjacent to the silicon due to stress. The pad oxide is then removed by a wet etch, which may cause the divot to grow. The gate oxide is then grown on the silicon wafer surface, and hi-k dielectric gate material is deposited. When the dielectric gate material is deposited, it will fill the divot, causing extra capacitance and possibly generating an out of control “foot short”. If a foot short is generated due to a divot filled with gate material, yields may plummet.